module fifo_syn_wraddr_gen(clk,
                           rst,
                           wr_en,
                           full,
                           wr_addr,
                                     wr_addr_r);
  input clk,rst,wr_en,full;
  output [5:0]wr_addr,wr_addr_r;
  
  reg [5:0]wr_addr,wr_addr_r;
  wire clk,rst,wr_en,full;
  
 always@(posedge clk )//or rst or full or wr_en)
   begin
     if(!rst)
       begin
         wr_addr=0;
       end
     else
       begin
         if(full)
           begin
             wr_addr[5:0]=6'b111111;
           end
         else
           begin
               if(wr_en)
                 begin
               // if(wr_addr_r<wr_addr)
                   wr_addr_r=wr_addr_r+1;
                   wr_addr=wr_addr+1;
                 end
           end
       end        
   end
endmodule
  

    
